1. Field of Invention
The present invention relates to a clock synchronization circuit. More particularly, the present invention relates to a delay locked loop (DLL) circuit and a method for eliminating jitter and offset therein.
2. Description of Related Art
Clock synchronization circuits are commonly used in electronic systems to provide good clock distribution, which is very important to overall performance of a product. Examples of such clock synchronization circuits include a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit. Conceptually, PLL and DLL circuits operate similarly. For DLL circuits, they include analog DLL circuits and digital DLL circuits, in which the analog DLL circuits have different performances from the digital DLL circuits.
FIG. 1 illustrates a typical analog DLL circuit. The analog DLL circuit 100 includes a phase-frequency detector (PFD) 102, a charge pump (CP) 104, a low pass filter (LPF) 106, a bias generator 108 and a voltage controlled delay line (VCDL) 110. The PFD 102 compares the phase difference between an input clock signal CKIN and a feedback clock signal CKON, and has two outputs UP and DN. The output of the PFD 102 is a pulse with a width equal to the amount by which CKIN leads or lags CKON. If CKIN leads CKON, the pulse appears on the UP output of the PFD 102. If CKIN lags CKON, the pulse appears on the DN output of the PFD 102.
The UP and DN outputs are input to the charge pump 104, and the charge pump 104 converts the input, either UP or DN, into an analog current for subsequent processing. The output current of the charge pump 104 is input to the LPF 106, and the LPF 106 functions to integrate the current output from the charge pump 104 to generate a control voltage VCTL. After that, the control voltage VCTL is input to the bias generator 108, and the bias generator 108 generates two outputs VBP and VBN according to the control voltage VCTL. Then, the VCDL 110 controls the frequency of the input clock signal CKIN based on the outputs VBP and VBN generated by the bias generator 108, so as to output N clock signals, i.e. CKO[1:N], that have different phases from each other, in which the output clock signal CKON is fed back to the PFD 102 to be compared.
However, the operation frequency of the analog DLL circuit 100 described above is still too high, such that the control voltage VCTL changes too fast and the analog DLL circuit 100 cannot work stably. Besides, the LPF 106 in the analog DLL circuit 100 is usually designed on a large area to suppress high frequency noise, thereby providing stability to the operation of the analog DLL circuit 100. Thus, the production cost and size of the analog DLL circuit 100 including the LPF 106 cannot be reduced.